Exegy is seeking an internal full-time hardware engineer for a position involving RTL and software co-design, implementation and verification. The engineer will have experience in the full FPGA design lifecycle including hardware architecture, RTL coding, simulation, system integration, hardware validation, verification, implementation and testing. This role will be eventually based at our headquarters in St. Louis MO.
Knowledge, Skills and Abilities:
- Experience working in Verilog is required.
- System Verilog experience is a plus.
- Experience with C++ is required.
- Experience working in a Linux environment.
- You will be comfortable with Python.
- Experience with Questa is a plus.
- Experience with Quartus and/or Vivado is a plus
- Exposure to network and system level protocols, packet based data processing, and computer architecture.
- BS or higher in Computer Engineering or Electrical Engineering and/or relevant industry experience.
- Catered lunches on Fridays, social events, and volunteering to engage with the community
- Weekly yoga, soccer games and happy hours
- A fridge of La Croix and other beverages (coffee, tea, energy drinks)
- Ping pong, foosball, and shuffleboard tables